|The RAMP（RAM Processor）series is developed for the application specific
embedded memory logic（EML）. In the RAMP-1, a single chip rendering engine,
that consists of a DRAM frame buffer, a SRAM serial access memory, pixel/edge
processor array and 32b RISC core, is proposed for low power 3D-graphics
in portable systems. Its main features are 2D-hierarchical octet tree（HOT）array
structure with bandwidth amplification, three dedicated network schemes,
virtual page mapping, memory-
||coupled logic pipeline, low power operation, 7.1GB/s memory bandwidth and 11.1Mpolygon/sec drawing speed. The 56mm2 prototype die integrating one edge processor, 8 pixel processors, 8 frame buffers and a RISC core is fabricated using 0.35mm CMOS EML（Embedded Memory Logic）technology. Successful 3D rendering operation is demonstrated by the test chip operation combined with a host PC through a PCI-bridge.