Greeting Outline
Outline

Name: Electronic Design and Solution Fair 2004 (EDSFair2004)
Objectives: The age of chips with millions of gates is at hand, and advanced development to upgrade device performance, reduce risks, costs and power consumption, and em-bed software is proceeding at an unprecedented pace around the world. Reflecting this trend, EDSFair assem-bles specialized information on advanced device tech-nologies, such as EDA, ASICs (Application Specific Inte-grated Circuits), FPGA/PLDs (Field Programmable Gate Array/Programmable Logic Devices), IP re-usage, embed-ded software and design services. Also featured are the latest trends and targets for further development of electronics technologies
Schedule: Thursday, January 29, & Friday, January 30, 2004
10:00 a.m. to 6:00 p.m.
Location: Pacifico Yokohama (Exhibition Hall, Annex Hall) 1-1-1,
Minato Mirai, Nishi-ku, Yokohama 220-0012
Admission: Exhibition: Free (registration required at show entrance) Conferences: Fees will be charged for some conferences
Sponsor: Japan Electronics and Information Technology Industries Association (JEITA)
Cooperation: Electronic Design Automation Consortium (EDAC)
Support:
(expected)
Ministry of the Economy, Trade and Industry, Japan (METI)
Embassy of the United States of America in Japan
Distributors Association of Foreign Semiconductors (DAFS)
City of Yokohama
Assistance:
(expected)
Institute of Electronics, Information and Communication Engineers (IEICE)
Information Processing Society of Japan (IPSJ)
Japan Printed Circuit Association (JPCA)
Management: Japan Electronics Show Association (JESA)


 
Back Page Top


Japan Electronics Show Association
Telephone : +81-3-5402-7601 Facsimile : +81-3-5402-7605 
http://www.jesa.or.jp
ALL Rights Reserved by Japan Electronics Show Association.