Electronic Design and Solution Fair 2007
 
VERIFIC DESIGN AUTOMATION 238
 
 
所在地 1516 Oak St., Suite 115, Alameda, CA 94501, USA
連絡先
TEL:1-510-522-1555
FAX:1-510-522-1553
E-mail:michiel@verific.com
URL:http://www.verific.com
出展物紹介 VERIFIC DESIGN AUTOMATION develops VERILOG, VHDL, and SYSTEMVERILOG parsers, analyzers, and elaborators for the EDA market. Our customers applications include synthesis, simulation, formal verification design for test, RTL debug, and virtual prototyping. Verfic licenses it's software royalty free and ships c++ source code to its customers.
   
   



 
 




日本エレクトロニクスショー協会
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http://www.jesa.or.jp
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