Home » Information for Exhibiting » Exhibition Outline

Exhibition Outline


The age of chips with millions of gates is at hand, and advanced development to upgrade device performance, reduce risks, costs and power consumption, and embed software is proceeding at an unprecedented pace around the world. Reflecting this trend, EDSFair assem- bles specialized information on advanced device technologies, such as EDA, ASICs (Application Specific Integrated Circuits), FPGA/PLDs (Field Programmable Gate Array/Programmable Logic Devices), IP re-usage, embedded software and design services. Also featured are the latest trends and targets for further development of electronics technologies.

Name: Electronic Design and Solution Fair 2007
Schedule: Thursday, January 25 & Friday, January 26, 2007
10:00 a.m. to 6:00 p.m
Location: Pacifico Yokohama (Exhibition Hall, Annex Hall)
1-1-1, Minato Mirai, Nishi-ku, Yokohama 220-0012
Admission: Exhibition: Free (registration required at show entrance)
Conferences: Fees will be charged for some conferences
Sponsor: Japan Electronics and Information Technology Industries Association
Cooperation: Electronic Design Automation Consortium
Support:(expected) Ministry of the Economy, Trade and Industry, Japan (METI)
Embassy of the United States of America in Japan
Distributors Association of Foreign Semiconductors (DAFS)
City of Yokohama
Assistance:(expected) Institute of Electronics, Information and Communication Engineers (IEICE) Information Processing Society of Japan (IPSJ) Japan Electronics Packaging and Circuits Association(JPCA)
Jointly held event: The 14th FPGA/PLD Design Conference
Concurrently held events: System Design Forum 2007
ASP-DAC 2007 (Asia and South Pacific Design Automation Conference 2007)
Management: Japan Electronics Show Association (JESA)