Home » Conference/Forum » System Design Forum 2009

System Design Forum 2009

JEITA EDA Technical Committee (EDA-TC) will host System Design Forum 2009 at Pacifico Yokohama, Japan. This year’s forum, consisting of 2 sessions, will be held January 23, 2009. The first session (10:00-12:00) will cover system-level design language (SystemC), some effective methods for addressing the design crisis of SoC (System-on-a-Chip). Easy-to-understand explanations of the latest standardization, STARC transaction-level modeling Guideline and introduction of the cutting-edge design examples will be given for SystemC.
The second session (12:45-16:30) will focus on predict of 32 nm process variations and design methodology in statistics from the perspective of cutting-edge, and introduce the current state of design methodology on considering variations.

Date Session 1 SystemC Users Forum 2009, January 23 (10:00-12:00)
Session 2 Nano-Scale Physical Design Forum, January 23 (12:45-16:30)

Annex Hall, Pacifico Yokohama (Floor Plan)

  Pre-Registration On-site Registration
Session 1 2,100 yen 2,625 yen
Session 2 3,150 yen 4,200 yen

On-line registration will be available from December 2008 at URL: http://www.edsfair.com/


Japan Electronics and Information Technology Industries Association (JEITA)


Open SystemC Initiative (OSCI)

  Note: Most of the presentations at the System Design Forum 2009 will be given in Japanese.

Session 1 SystemC Users Forum 2009

Date January 23 (10:00-12:00)

Chair: T.Hasegawa (JEITA SystemC Working Group)

On December 12, 2005, IEEE approved SystemC (IEEE Std. 1666-2005). Since then, SystemC that is a C-based language, has been widely used as a standard language for both verification and system-level design flows in the fields of both verification and design. Included in this session are: 1) Update of SystemC current status and road map, presented by OSCI, 2) Easy-to-understand explanations of STARC transaction-level modeling Guideline, and 3) Examples of design-related SystemC.

Session 2 Nano-Scale Physical Design Forum

Date January 23 (12:45-16:30)

Chair: T. Kanamoto (JEITA Nano-Scale Physical Design Working Group)

Along with recent advances in semiconductor devices and interconnection technologies, new issues are emerging in current design methodology. Various approaches, such as new libraries or design schemes, have been developed to solve these issues but left un-standardized even after those become commonplace. It prevents semiconductor manufacturers and their customers from smooth exchanging design information.

In this session, the following topics will be presented to overview the current status of variation-aware design methodology: 1) Variations of device characteristics in the process of next-generation, 2) Variations of circuit characteristics in the process of next-generation, 3) Process variations of SRAM and design methodology in statistics from the perspective of cutting-edge, 4) Design methodology for reduce variation and variations in statistics.