Electronic Design and Solution Fair 2009
 
TANNER RESEARCH JAPAN K.K. 707
 
 
Location BUREX Kojimachi 6F, 3-5-2 Kojimachi, Chiyoda-ku, Tokyo
102-0083
Contact info Sales Deptartment
TEL:03-3239-2840
FAX:03-3239-2860
E-mail:sales.jp@tanner.com
URL:http://www.tanner.jp
Exhibit introduction Tanner EDA solutions offer "perfect combination of PRICE and PERFORMANCE" and "total solution for Analog IC Design".
Our solutions include tools for:
¡¡Schematic Capture
¡¡HSPICE compatible Simulator
¡¡Physical Layout
¡¡Physical Verification - DRC, Extract, LVS and R/C Parasitic Layout Extraction
Designer can build cost effective design environment with all the necessary functions for Analog IC design!
   
   



 




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