Electronic Design and Solution Fair 2009
 
nSys Design Systems Pvt Ltd [Emerging Company Area] 201
 
 
Location Delhi
110034-
Contact info Atul Bhatia
707, B-09, ITL Twin Tower, Netaji Subhash Place, Pitam Pura, Delhi 110034
Phone: 91-11-27354994, 91-11-47572300
TEL:91-11-47572300
FAX:1-888-679-7462
E-mail:atul@nsysinc.com
URL:http://www.nsysinc.com
Exhibit introduction Japan First New Product
nSys offers the World's largest portfolio of Verification IPs and also leverages them to provide Verification Services that Accelerate designs of customers developing ASIC/SoC/FPGA, while lowering their costs and risks.


Verification IPs:

Hundreds of ASIC/FPGA developers worldwide are using the nVS family & benefit from the widely accepted & proven Verification IPs for following standard interfaces/protocols.

Every nVS consists of BFMs, Monitors, Assertions-based Checkers and Test Suites.

* PCI(tm): PCI Express(r) Gen2/Gen1, SR-IOV , PCI-X(tm), PCI

* ARM AMBA(tm): AXI, AHB, APB

* Storage: SATA, SAS, ATAPI

* Communication: Ethernet 40G/10G/1G, SPI 4.2

* Memory: DDR3, DDR2

* Consumer: USB3.0, USB 2.0, WUSB

* Others: SDIO, UART, I2C, SMBus, PCMCIA, IEEE1284, ASI

* Available in native SystemVerilog, Verilog, VHDL and with wrappers for Vera, SystemC and e



Verification Services:

nSys uses its extensive verification experience, knowledge of standards, portfolio of Verification IPs and customer orientation to help development teams with specialized services targeted at different development phases.

* Independent Verification: Protocol Compliance, SoC Verification

* SystemVerilog Migration: Testbench, Methodology, Verification IP Porting
   
   



 




Japan Electronics Show Association (JESA)
phone : 03-5402-7601 FAX:03-5402-7605
http://www.jesa.or.jp
ALL Rights Reserved by Japan Electronics Show Association
This site is confirmed to work properly on IE5.0, NN4.7
and their respective latter versions.