Electronic Design and Solution Fair 2009
Gem Design Technologies, Inc. [JEVeC Village] 411
Location 1-8 Hibikino, Wakamatsu, Kitakyushu, Fukuoka, Japan
Contact info Gem Design Technologies, Inc.
Hiroshi Murata
Exhibit introduction World First
We present the latest version of SiP Feasibility Study Tool "GemPackage". This product enables you to examine if your SiP is possible, before going into the detailed design phase, by providing following functionalities.
- Quick wire/FC bonding design
- Semi-auto interposer routability analysis
- Chip-Package-Board super hierarchical view
- 3D observation using Google Earth/SketchUp
- Link to CAD systems (Cadence APD)
- Link to EM analysis tools (Ansoft HFSS,TPA,etc)
- For FBGA, PBGA, SiP, MCM, PoP, Si-Interposer


Japan Electronics Show Association (JESA)
phone : 03-5402-7601 FAX:03-5402-7605
ALL Rights Reserved by Japan Electronics Show Association
This site is confirmed to work properly on IE5.0, NN4.7
and their respective latter versions.