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Concierge Service

Concierge Service is for engaged visitors involved in design or design environment configuration to visit booths effectively.

For the issues which engineers face, we offer 30 Guide Maps with each theme.
(The map will be uploaded to EDSFair Official Website on Jan.15th.)
The exhibitor information according to the theme you checked will be sent you in advance.

Thematic Guide Maps which are easy to distinguish solution you want enable you to visit booths effectively even if you are pressed for time.

Theme registration is available at the pre-registration page.

Register Here
Register solutions ( for Exhibitor )

Concierge Service The 30 Themes

No. Themes
1 Method(s) for CMOS-MEMS Concerted Simulation
2 Faster HW/SW Co-verification tool
3 All-in-one packaging design technology for chip/package/board
4 TLM2.0-compliant System level design technology
5 OVM/VMM compliant verification tool and library
6 Verification technology using ASIC prototyping
7 Implementation method for higher-accuracy power consumption estimate in early design stage
8 GALS design technology by dynamic voltage control
9 Effective low power method during each stage of design flows
10 Die-size reduction through power design optimization
11 Die-size reduction through memory optimization in SoC
12 Die-size reduction through number of bit optimization of processor
13 Process Technology for 32nm
14 Device-size minimization through high voltage device process
15 High speed AD and high speed analog circuitry technology
16 32nm, 22nm RF CMOS design technology
17 Simulation Technology for MMW RF circuit
18 High speed simulation technology for PLL
19 Easily-testable technology for Mixed Signal design (Design for testability of Mixed Signal?)
20 Test cost reduction method
21 Technology to facilitate identification of defect spots
22 Method of temperature failure analysis
23 Case example of timing closure using SSTA
24 High speed interface design technology for PCI Express/SATA/USB
25 High speed memory interface design technology for DDR3/2/LPDDR2
26 SiP design technology equipped with DDR3 333/500MHz memory
27 Thermal analysis method for chip package
28 Effective management method of IP and design re-use
29 Effectiveness of DFM such as double-via technology, etc.
30 EDSFair first time exhibitor or Company inaugurated within one year.