Electronic Design and Solution Fair 2009
NOAH Corporation
所在地 〒222-0033
4F NARA BUILDING II 2-2-8, Shinyokohama,
Kohoku-ku, Yokohama, Kanagawa 222-0033
連絡先 ソフトウェアビジネスユニット
Software Business Unit
出展物紹介 LogicVision社製:「ETMemory、ETLogic、他」
大規模、高集積化するSoC に対し、実速度での高品質なテストを可能にし、テストコストを大幅に削減することができます。メモリテスト向け、ロジックテスト向け、その他 LogicVision社のEmbedded Test Solutionをご紹介いたします。

Nascentric社製:「Omegasim、OmegaSim AMS、 OmegaSim GX」
フルチップデザインに対応可能な高速/高精度の Rocket Fast SPICEシミュレータをご紹介いたします。OmegaSim GXは、nVidea社GPUによるハードウェア・アクセラレーションに初めて対応した製品です。

Javelin Design Automation社製:「TrueFit、TruePlan、TruePro」
SoC 開発の初期段階からチップの出来上がりをイメージし、得られる各種情報は設計フローの出戻りを大幅に削減します。これらの情報を単一データベースで管理、共有できるJ360 System Physical Prototypingをご紹介いたします。

LogicVision, Inc. : "ETMemory, ETLogic, etc."
LogicVision provides embedded test solutions that enable its customer to achieve very high device quality metrics, reduce overall cost of test, accelerate silicon bring-up and improve production and yield ramp times.

Nascentric, Inc. :"Omegasim, OmegaSim AMS, OmegaSim GX"
Nascentric provide the fastest, highest capacity, and most accurate SPICE verification and analysis for complex nanometer designs. OmegaSim GX is the 1st hardware-accelerated SPICE simulator in the world.

Javelin Design Automation : "TrueFit, TruePlan, TruePro"
J360 System Physical Prototyping that consists of product families; TrueFit, TruePlan and TruePro delivers accurate physical feasibility feedback from the earliest architecture stage and efficient collaboration of architectural, logic and physical design data.
1月22日(木) 時間:13:30 〜 14:15   会場:DM5
Low DPM Logic Test

David Buck
Senior Director
Applications Engineering
LogicVision, Inc
There is growing evidence that many different defect types are becoming prominent at the newer technology nodes. There is now a general consensus that the traditional approach of simply targeting stuck-at faults is no longer sufficient. This presentation will explain how LogicVision's ETLogic and ScanBurst products, both part of the new Dragonfly Test Platform, enable very low DPM logic testing.
1月23日(金) 時間:14:30 〜 15:15   会場:DM1
Nascentric OmegaSim GX and NVIDIA Tesla Computing Processor speeds accurate SPICE simulation of large mixed-signal circuit

Dr. John Croix & Rahm Shastry
Dr. John Croix: Founder and CTO
Rahm Shastry: President and CEO
GPU (Graphical Processing Unit) Computing Processors have customarily found applications in high performance computing graphics and the video game industry. GPUs have two characteristic of interest to the EDA simulation world - they are made up of massively parallel floating-point compute element and they are inexpensive. SPICE simulates the nonlinear time-variant behavior of a circuit. SPICE is increasingly running out of steam to accurately and rapidly address large, complex mixed-signal circuits which may consist of millions of transistors and RC parasitic. On the other hand, the traditional Fast-SPICE simulators do not offer the accuracy required for circuits built using 65nm and below process nodes. Nascentric's OmegaSim GX simulator is the first product that leverages the massive parallelism of NVIDIA Tesla GPU Computing Processors to accelerate SPICE simulation of large mixed-signal designs. OmegaSim GX can now not only utilize the GPU to accelerate the transistor evaluations in a circuit, but it also offloads the core simulation solver as necessary onto the GPU. The second generation OmegaSim GX now also addresses single-CPU/multi-GPU configuration. In this seminar, we will discuss and demonstrate OmegaSim GX use model as well as discuss the results of customer benchmarks that illustrates the acceleration that has been achieved to date. We will also discuss the types of circuits that benefits from using OmegaSim GX.
1月23日(金) 時間:15:30 〜 16:15   会場:DM2
2D and 3D pathfinding: A new methodology that delivers 8X productivity gain in concurrent tuning and optimization of underlying System Architecture, RTL Design and Silicon technologies for advanced SoC design
Roger Carpenter
Chief Technical Office (CTO)
Javelin Design Automation, inc.
Presenting the j360 Silicon PathFinder from system design to RTL; with placement, routing, timing, pin assignment, and post-placement optimization. Handling black-box, ESL, to RTL, or gate. Virtual LEF Generation. Create a System Physical Prototype for architecture, design, library and process impact on timing, power, congestion, and yield. Fully hierarchical and supporting sub-100 nanometer technology to a billion plus gates.



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