Exhibitor Detail : The University of Tokyo VDEC
VLSI Design and Education Center (VDEC), which is located in the University of Tokyo and shared by users all over Japan, was established in May, 1996. As an intellectual education center on VLSI technology, VDEC aims at improvements of instruction on VLSI design and supports on VLSI chip fabrication for national universities, public universities, private universities and colleges in Japan. For these purposes, VDEC performs various kinds of activities including distributing VLSI design information, providing CAD software and licenses and supporting chip fabrications. With helps and supports from universities, related government ministries and semiconductor industry, active services provided by VDEC have been growing extensively since its beginning.
Nowadays, wide variety of VLSI fabrication technologies including 65nm to 1.2um, various kinds of popular CAD software, and mesurement facilities are provided through VDEC.
2-11-16 Yayoi Bunkyo-ku, Tokyo
Room411, Takeda Bldg., Univ. of Tokyo