Exhibitor Detail : Waseda University Goto Lab, Watanabe Lab, Kimura Lab, Yoshimura Lab
As the Semiconductor technology enters the nanometer era, System LSI design is confronted with a crisis due to not only the circuit scale and complexity but also the rapidly growing power densities and interconnect (wire) latency. Those critical issues are also bottlenecks for promoting the system performance.
Here, we will show some recent progress of research and development on Nanoscale CMOS system oriented design techniques in Graduate School of IPS.
- Fine-grain power gating optimization under timing constraints,
- Assertion synthesis for prototyping verification,
- An efficient floorplan algorithm which determines the abstract location of macro blocks,
- A high-level scheduling method and DFM,
- Customizable processor-IP and its design environment,
- Network-on-Chip applied for Hardware Neural Network,
- Some prototyping of Multi-processor SoC
[These R&D are partly supported by a grant of Knowledge Cluster Initiative 2nd stage of MEXT]
Hibikino 2-7, Wakamatsu-ku, Kitakyushu-shi, Fukuoka-ken, 808-0135, Japan