• Home
  • What's EDSFair
  • Exhibitors
  • Exhibitor Seminar Search
  • Special Stage
  • Special Zone
  • FPGA/PLD Design Conference
  • Access / Accommodation
  • Press Room
  • Contact

 Exhibitor Detail : A-R-Tec Corp.
118 

A-R-Tec Corp.
New Product

Exhibit introduction

1. Si Substrate and Power Supply Noise Analysis Tools
-FPNA: Floor Plan Noise Analysis
-GDSNA: GDS Noise Anaylsis
2. System level Xtalk Noise Analysis Services
-Noise Analysis and Model Generation
-On Chip Noise Monitor Macro Design and Measurment
-AMS Chip Design Support using Commercial Tools
3. Analog Macro Development -OPA, ADC, DAC
4. Custom Sensor Development -Image, X-Ray
5. MEMS Sensor Interface Development -CV Converter
6. On the Job Training of Analog Circuit Designer


Contact info

Atsushi Iwata/Head Quarter
TEL:082-422-8378
FAX:082-422-8378
E-mail:iwa@a-r-tec.jp
URL:http://www.a-r-tec.jp

Address

10-29-1205, Saijo-Otsubo-cho, Higashi-Hiroshima, JAPAN
739-0005

Back to exhibit list