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Atrenta SpyGlass Solutions for Early Testability and Low Power Design Adopted by NEC Electronics

  Tokyo, Japan January 26, 2010 -- Atrenta Inc., the leading provider of Early Design Closure solutions to radically improve design efficiency throughout the IC design flow, today announced that NEC Electronics Corporation has adopted the SpyGlass-Power solution for RTL power estimation and reduction, as well as the SpyGlass-DFT solution for early testability analysis.

  Atrenta’s SpyGlass-Power solution provides early information about power consumption at RTL, and provides guidance for power reduction with respect to clock gating, memory and data path designs. The solution not only detects, but can also automatically fix key power management issues. The SpyGlass-Power solution supports UPF and CPF power formats and verifies designs with voltage and power domain management structures so that voltage level shifters and isolation logic are correct.

  The SpyGlass-DFT solution has the unique ability to predict ATPG (automatic test pattern generation) test coverage for both stuck-at and transition faults and pinpoint testability issues as the RTL description is developed, even before a gate-level netlist is generated. The SpyGlass-DFT solution not only detects testability issues--it can also automatically correct them.

  “By using SpyGlass-Power for RTL level analysis and efficient clock gating, we were able to reduce power by up to 40% in our wireless chip,” said Akira Denda, Department manager, Device Platform Development Department 1st SoC Operations Unit at NEC Electronics Corporation. “The SpyGlass-DFT solution enabled us to catch testability issues early at RTL, and improve the test coverage by over 20%. We are very pleased with the SpyGlass results on our chip designs.”

  “Power is one of the key design challenges for advanced chip designs and our customers are looking for solutions that can save multiple iterations of synthesis and costly power simulations at the gate level. We are pleased to see an increasing adoption of the SpyGlass-Power solution by leading semiconductor companies like NEC Electronics to address this critical need,” said Mike Gianfagna, vice president of marketing at Atrenta. “This decision, along with NEC Electronics’ adoption of the SpyGlass-DFT solution represent strong validation of our industry-leading solutions for RTL testability and power analysis.”


  About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. For more information, visit www.atrenta.com. Atrenta, Right from the Start!

For more info, please contact:

Atrenta Corporate:
Charu Puri, Corporate Marketing
Atrenta Inc.
Email: cpuri@atrenta.com
Tel: +1-408-467-4254

Atrenta PR Agency:
Ed Lee
Lee PR
Email: ed@leepr.com
Tel: +1-650-363-0142

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Atrenta, the Atrenta logo, SpyGlass, and Early Design Closure are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.