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 出展者詳細 広島大学 アルゴリズム論研究室

広島大学 アルゴリズム論研究室
Laboratory of Algorithm Engineering, Hiroshima University






MULTI-PRIDE is a system for supporting multi-layered printed wiring board design. It consists of
(i) circuit bipartition,
(ii) placement and routing on each outside layer,
(iii) modification of wiring and compaction,
(iv) routing on inside layers, and
(v) parallel processing for routing.

We have been developing MUTI-PRIDE as a system for interactively supporting printed wiring board design. This is because there are too many restrictions and conditions to be met by a complete automatic designing system.

MULTI-PRIDE constructs one printed wiring board consisting of n layers for n >= 1. When n=1, only one layer (called an outside layer) is used for placement and routing, and unsatisfied connection requirements are realized as jumpers. When n=2, the one layer is used for placement and routing, and there is choice for the other layer: it is used for realizing unsatisfied connection requirements left on the the first layer, or it is used for both placement and routing. When n>=3, the first and the last layers are called outside layers, and any other layer is called an inside layer that is exclusively used for routing. Elements (ICs, resistors, capacitors, and so on) are placed on one or both of the outside layers and routing is done on outside layers and/or inside layers. Inside layers are to be provided if any connection requirement remains unsatisfied after routing on outside layers: inside layers are added one by one until all connection requirements are satisfied.

The main point of MULTI-PRIDE is that placement and routing can be done simultaneously so that the number of jumpers or wiring on inside layers may be reduced.

On the other hand, there is still room for improvement: it is likely to produce layouts that are larger than expected, and it is not necessarily easy to place elements at specified locations of boards.

As improvement, compaction of layouts by modifying placement and routing with physical conditions maintained has been implemented. We are going to implement functions of placing some elements to the border of a board.


広島大学 大学院工学研究科情報工学専攻
Department of Information Engineering, Graduate School of Engineering, Hiroshima University
TEL:082-424-7662   FAX:082-422-7028


Kagamiyama 1-4-1, Higashi-Hiroshima City,
Hiroshima, Japan

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