Blue Pearl Software provides tools which lower design risk, improve the quality of results, save time and reduce the cost of their chip design process.
Blue Pearl Software's RTL Analysis technology automatically checks HDL for compliance with user-selected and user-defined properties, including netlist checks and advanced property checks for CDC.
Blue Pearl's Timing Constraint Generation and Management reads RTL and statically identifies complex false and multicycle paths that occur due to complex control logic. Blue Pearl writes SDC, and writes assertions for testing paths with formal analysis tools. Blue Pearl also merges and compares SDC and migrates constraints up and down the design hierarchy.
Blue Pearl's Timing Constraint Validation reads SDC files and validates them using Blue Pearl's powerful state space search technology. If paths are found invalid Blue Pearl outputs a testbench and patterns that show how invalid paths can be sensitized.
These three technologies have been integrated into a single executable program (The Blue Pearl Software Suite) for fast design analysis, CDC checking, and timing constraint generation, management, and validation.
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