Exhibitor Detail : The University of Aizu, Saito Laboratory
315 

The University of Aizu, Saito Laboratory

Exhibit introduction

Different from synchronous circuits where circuit components are controlled by global clock signals, circuit components in asynchronous circuits are controlled by pairs of local handshake signals with request and acknowledge signals if required.ĦĦAlthough asynchronous circuits are potentially low power consumption and low electro-magnetic emission, the design of asynchronous circuits is difficult. From the design requirements, appropriate delay model, control protocol, data encoding scheme must be selected.
In our laboratory, we are developing a design environment for asynchronous circuits with bundled-data implementation. In bundled-data implementation, data-paths are designed with the same resources as synchronous ones and they are controlled by asynchronous controllers.
In this EDS Fair, we are going to exhibit a behavioral synthesis tool for bundled-data implementation which synthesizes an RTL model from a behavioral model of an application specified by the C language and a constraint generation tool which generates constraints for logic synthesis and physical synthesis tools.


Contact info

The University of Aizu
TEL:(0242)37-2576
FAX:(0242)37-2598
E-mail:hiroshis@u-aizu.ac.jp
URL:cldr02.u-aizu.ac.jp

Address

Tsuruga, Ikki-machi, Aizu-Wakamatsu, Fukushima, Japan
965-8580

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