In low power designs, the power consumption in test mode is much higher than in functional mode, and yield loss may be caused by this high test power consumption. High power consumption increases gate-delay due to excessive IR-Drop. Especially, during at-speed-testing, excessive gate-delay can cause over-testing which means that a good-chip is falsely regarded as a faulty-chip. Thus, to avoid over-testing, test power in a circuit must be analyzed and reduced if necessary. In addition, shipped chips are taking risk of field reliability with rapidly reducing marginality due to increasing process variations and degradation mechanisms (e.g. NBTI, HCI, TDDB), which are difficult to detect in fabrication test. Therefore, some kinds of methodologies that guarantee quality in the field are strongly required. This exhibition shows low capture power testing techniques based-on test pattern generation and field testing techniques for detecting aging-induced faults.
Kyushu Institute of Technology
680-4 Kawazu, Iizuka-shi, Fukuoka, JAPAN