Exhibitor Detail : Aldec-Japan K.K.
204 

Aldec-Japan K.K.

Exhibit introduction

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1) HES (Simulation Accelerator)
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Target:
*For PM and VE, who are not satisfied with performance of simulator
but difficult to pay for another resources

Features:
*Best for verification of high performance image, video and communication
processing HW modules/core/IP
*Automatically importing simulation environment and building acceleration
environment
*10 to 100 times faster than simulation
*Windows/Linux platform support

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2) ALINT (RTL lint checker)
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Target:
*For PM, HD and VE who need to improve design quality and exchange designs
between other teams

Features:
*The only windows and linux platform support STARC rule checker
*Automatic documentation for several teams and clients
*Intuitive operation possible with GUI
*PBL(Phase Based Linting)

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3) Riviera-PRO (Methodology driven fast simulator)
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Target:
*For PM, HD and VE who want to adopt latest verification methodologies including UVM/OVM/PSL and SVA

Features:
*UVM/OVM/PSL/SystemVerilog/SystemC/VHDL/Verilog
*3 times faster than market standard FPGA simulator
*Multi tasking for faster performance

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4) Active-HDL (Design creation and verification for FPGA designer)
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Target:
*For PM and HD who need automatic documentation and want to build FPGA development flow

Features:
*Waveform based test bench modification
*Automatic documentation with RTL import
*Project oriented design and verification flow management
*Intuitive operation from GUI without having training


Contact info


TEL:03-5312-1791
FAX:03-5312-1795
E-mail:sales-jp@aldec.com
URL:http://www.aldec.co.jp/

Address

Shinjyuku Estate Bldg. 9F, Shinjyuku, shinjyuku-ku, Tokyo 160-0022 JAPAN
160-0022

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