We will be presenting a cost-performance effective RTL design tool that runs under Windows and Linux. The design tool composes a versatile RTL inspection tool, a Verilog simulator, and a Verilog documentation tool. The inspection tool utilizes highly efficient and accurate quick logic synthesis technique and provides detail analysis report on the design written in Verilog HDL. The simulator executes Verilog HDL specification by transforming it to optimized intermediate object code. The documentation tool extracts design specification from Verilog HDL source description and generates HTML files that can be viewed with your favorite internet browser. We will be showing the design tool under Windows at our booth.
8-14-1 Tateishi, Katsushikaku-ku,