Exhibit introduction

Our general research interests are test generation and fault diagnosis for high-speed, deep-sub micron chips. Based on following competitive research grants, we are investigating techniques to make the test generation and fault diagnosis tools efficient for small delay faults and open faults.

1)Joint Research of Semiconductor Technology Academic Research Center (STARC)
Teat generation tool for open faults
Fault diagnosis tool for open faults
2)Contract Research of STARC
Fault diagnosis tool for small delay faults
Diagnostic test generation tool for transition delay fault
3)Grant-in-Aid Scientific Research
Defect-aware test generation tool
Test generation tool for faults on clock lines