K-Router: A newly born multi-net ultra high speed & success-rate router
Routing for the board design such as SiP's interposer routing, PCB's BGA escaping, FPGA's routing, are critical but current poor productivity by the manual design is bankrupting. Co-design for this situation depends on the performance of the router connecting different designs but hopeless.
K-router was born after four years to rescue this situation. It is a born multi-net router. Its power is, you believe or not, monstrous; Demonstration includes (a) 1000 pin BGA is escaped with all layers completely routed, in 10 seconds. If it is 10,000 pins, only several minutes. (b) A 100 random pin interposer is completed in less than 0.1 second. You will see how wire density changes as the pin location changes. c) For net-list routing, a tangle resolution circuit is visualized which is an image of hard design.
K-router, after the history of a half century for automation, will deal a new routing principle. It is a baby not yet a tool for industry will take place of the major principle in the future design.
Faculty of Environmental Engineering,
The University of Kitakyushu
1-1 Hibikino, Wakamatsu-ku,