Exhibit introduction

Closing timing has become increasingly challenging for designers.
Constraining synthesis to achieve required timing is a very tedious and repetitive process whereby the designer has to manually create the SDC constraints. However in today's designs, especially low power ones, the manual SDC creation flow has reached its limits because there can be tens of thousands of clock domain crossings (CDC) and False Paths (FP) and Multi-Cycle Paths (MCP). What designers need are tools that can produce better results, automatically and in a more comprehensive manner, as compared to the common, iterative manual approach. The ultimate benefit of Blue Pearl is that it automates the constraint creation process, allowing designers to achieve timing closure faster, while reducing design risk.