Exhibitor Detail : Aldec-Japan K.K.

Aldec-Japan K.K.

Exhibit introduction

For the purpose of design quality improvement and reuse many companies have adopted STARC RTL design style guide. However many problems due to design rule violation have still occurred during simulation and actual machine operation, so it takes a lot of man-hour to check the problem. ALINT has supported several kinds of rule sets including STARC rules. ALINT users can check coding style and utilize easy-to-use GUI to resolve design rule violations at early design stage.

* Riviera-PRO
Riviera-PRO is high-speed logic simulator which supports all of standard languages used for HDL design and both Linux/Windows 32bit/64bit platform. Powerful debugging features such as accelerated waveform viewer, code coverage, advanced dataflow, leading-edge verification methodology like assertion and OVM/UVM are supported. Riviera-PRO users can use C/C++/DPI-C/SystemC and MATLAB/Simulink interface to run co-simulation easily. In addition multi CPU supported simulation can significantly reduce simulation run time.

* Active-HDL
Active-HDL is design creation tool which provides both graphical entry like block diagram/state machine and integrated high-speed simulator for standard design languages. Design process management functionalities such as documentation, design flow manager and interface of revision control tools are provided. Active-HDL can work with FPGA vendor tools and encrypted source code like Xilinx SecureIP can be run. Active-HDL users can use various proven features to develop design efficiently.

Over 10 years has passed since FPGA based emulator has been introduced in the market as HW logic verification and/or software development support environment.
However many project managers are still not positive for its adoption or FPGA based emulator users have no other choice to move toward more expensive emulator based on custom chip.
Two major reasons of those same situation are shown below:

1)Building emulation environment needed more resources than expected, so as a result TAT could not be reduced.
2)Emulation environment has been built but target speed could not achieve. Therefore only some verification items could be performed.

Aldec's emulation environment "HES" is the only platform running on both Windows and Linux. HES brings verification environment compatible with software development environment.
In addition HES provides patented clock handling technologies and SCE-MI infrastructure based transactors. Aldec accelerates customer's emulation based verification methodology adoption.

* Hardware/Software Co-verification System for Embedded System
(Reference Exhibit by Meidensha Corporation ("MEIDEN"))

In the development of embedded systems, as the embedded systems become more functional and compact, the actual verification on the embedded system is getting extremely difficult.

This system is for hardware/software co-verification. By using a high-speed logic simulator ( Riviera-PRO, Active-HDL or others), it could perform simulation upon the embedded board. By using this system, the user can make an effective debugging of the program or device on the board.

This system could run the softwares written for Renesas Electronics' SH-2 and SH-2A RISC engines.

Contact at MEIDEN on this Web Info:

Fumihiko Mori
ICT Promotion Center
System Technology Research Laboratories
Research & Development Group
Meidensha Corporation
E-mail mori-f@mb.meidensha.co.jp

Contact info



Shinjuku Estate Bldg. 9F, 1-34-15 Shinjuku, Shinjuku-ku, Tokyo

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