Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 150 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Asia. Visit www.jasper-da.com to reduce risks; increase design, verification and reuse productivity; and accelerate time to market.
|時間：10:00 〜 10:45
Leveraging Jasper Formal Verification Throughout the Entire Design Cycle
Vice President of Marketing and Business Development, Jasper Design Automation Inc.
The adoption of formal verification technologies is increasing as designs become more complex. Jasper Design Automation’s unique and powerful formal technologies break through to go beyond typical formal solutions to address a wide range of applications. With Jasper’s solutions, the benefits of formal technology can now been reaped throughout all design and verification stages including:
・ Stand-alone verification of architectural protocols
・ Designer sandbox testing for RTL development
・ End-to-end data packet integrity
・ SoC connectivity and integration verification
・ Root-cause isolation and full proofs during post-silicon debug
・ Property Synthesis and coverage closure
Jasper’s formal verification is a valuable addition to traditional verification methods. For example, applying Jasper’s formal techniques early in the design cycle to exhaustively verifying block-level design functionality can produce higher quality RTL delivered to unit and system level verification. Attendees will learn about unique Jasper formal technologies and flows that enable designers and verification engineers to augment existing flows. Also included will be discussions about how effort applied to one application can be leveraged in others. When applied intelligently, Jasper formal technologies can enhance traditional design and verification flows to help reduce the risks associated with increasing SoC complexity.
707 California Street
Mountain View, CA 94041