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Special Stage

January 29, 2009

Low power is a keyword for Green society and low-power design is one of the hottest themes in LSI design today. Panelists from semiconductor vendors, EDA vendors, and a member of JEITA STRJ WG1 will discuss about the present status, issues and potential solutions for low-power design from various viewpoints. Comprehensive knowledge for low-power design will be obtained. Please join us.

[11:50-12:50]
Session4 | Low Power Design Session
*Simultaneous translation will be provided.

How to approach the issues regarding low-power designs shown in sesion3 will be presented by EDA vendors. Each vendor will show the current/future low-power design techniques. Whole picture of low-power designs will be revealed by session 3 & 4.

Chairperson
Mr. Ikutaro Kojima [Nikkei Business Publications, Inc.]
Panelists
Mr. Vic Kulkarni [Apache Design Solutions Inc., GM and SVP of RTL Business unit]
Dr. Bernard Murphy [Atrenta Inc., CTO]
Mr. Neil Hand [Cadence Design Systems Inc., Director, Solutions Marketing, Low power]
Dr. Anmol Mathur [Calypto Design Systems, CTO and Founder]
Mr, Robert Smith [Magma Design Automation, Inc., VP, Product Marketing]
Mr. Simon Bloch [Mentor Graphics Corporation, VP and GM, Design & Synthesis Division]
Mr. George Zafiropoulos [Synopsys, Inc., VP, Solution Marketing]
Mr. Mikio Sumatani [JEITA STRJ WG1, member, Semiconductor Company, Panasonic Corporation, GM]
Organizer
Mr. Masaaki Yoshida [NEC Electronics Corporation]
Mr. Toshinori Inoshit [Renesas Technology Corp.]

This session covers power and high-voltage analog circuits, and will be of interest to system LSI design engineers and to managers as well as to analog circuit design engineers, and all of you are welcome.

[15:30-17:00]
Session5 | Low Power Design Session
*Simultaneous translation will be provided.

Power-saving and environment-friendly developments, and development of low-power mobile devices, are very much in the news nowadays. This session covers related recent research and development - as well as future direction - into power and high-voltage analog circuitry. Topics will include high-efficiency power-supply circuit technologies for cellular phones and notebook PCs, and power amplifiers for base stations.
Issues and challenges of circuitry, device design and design automation technologies in this area will be discussed with a panel of experts.

Chairperson
Dr. Haruo Kobayashi [Gunma University, Electronic Engineering Department]
Panelists
Dr. Kenichi Onda [Hitachi, Ltd., Hitachi Research Laboratory.]
Dr. Jun-ichi Matsuda [Asahi Kasei Toko Power Devices Corporation]
Dr. Shigeru Nakajima [Sumitomo Electric Industries, Ltd., Transmission R&D Laboratories]
Mr. Nobuhisa Sato [Cadence Design Systems, Japan Mixed-Signal Implementation, Technical Field Operations]
Mr. Ernie Koeroghlian [Mentor Graphics Corporation, Product Architect, DSM CICD R&D]
Organizer
Mr. Kazuya Morii [SANYO Semiconductor Co., Ltd.]
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